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|
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 600
mils package size
|
 |
| |
40\42
pin counts
|
| |
70
mils and 100 mils lead pitch
|
| |
•
Full
in house design ability
|
| |
JEDEC
standard outlines
|
| |
|
|
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| |
Logic
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 |
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Memory
|
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Power
IC
|
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Process of P-DIP/SHRINK with BOM |
|
Process
flow
|
Material
|
|
Wafer Back
Grinding
|
|
|
Wafer Mount
|
|
|
Wafer Saw
|
|
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2nd Optical
Inspection
|
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Die Bond
|
|
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Epoxy Curing
|
|
|
Wire Bond
|
Gold wire
|
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Molding
|
compound
|
|
|
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Marking
|
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Sn |
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FVI
|
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Packing
|
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P-DIP/SHRINK Reliability Test
|
•Moisture
Sensitivity Test: JEDEC Level 3
(30℃
85%RH 168hrs)
|
•
•Temperature
Cycle Test: JESD22-A104C
(-65℃/5min~150℃/5min
500cycles)
|
•
•Pressure
Cooker: JESD22-A102-C
(121℃
2 atm 100%RH 168hrs)
|
•
•High
Temperature Storage Life: JESD22-A103C
(150℃
1000hrs)
|
