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Building Tomorrow's Solutions Today: 
Continuous R&D for Optimal Testing

Advanced Test R&D

map ate for soc

MAP ATE For SoC

sg9000 ate for rf devices

SG9000 ATE For
RF Devices

test rd center

Test RD Center

test technical committee

Test Technical
Committee

related test accessories design

Related Test
Accessories Design

test program development

Tester Platform
Development & Conversion

MAP SoC Test System

  • 100/200 MHz test rate
  • 1024 digital channel (Max. 1216 digital channel )
  • All in one: digital 64ch, DPS 8ch, BPMU 1ch & TMU 4ch per board
  • 256 sites parallel test
  • 512M pattern memory
  • 4K capture memory
  • Flexible architecture (any slot, any instrument)
  • Edge Resolution TS0: 4.5ps , other TS1 ~31: 250ps
  • Support STDF / Dynamic PAT
  • C/C++ development environment
  • AWG/Digitizer
  • RF integration
  • High density DPS

 

map soc test system

 

map soc test system

SG9000

 

Features

 

  • Sigurd designs RF-subsystem, ready for complete S-parameter testing
  • Covering from sub-6 GHz up to mmWave for Satcom and 5G application
  • Sigurd self builds production-oriented software, Dynamic PAT embedded in SG9000 OS
  • Truly parallel architecture as well as per-site independent testingfor special requirement

Target Market with Successful Projects

 

  • RF front-end : PA, switches, and FEM
  • mmWave : Radar and Beamformer for Satcom/5G
  • RFSoC : Tuner/BT/WiFi RF IoT, with Sigurd MAP integrated 

Technical support and customer service

 

 technical support and customer service

 

Combining customer needs with decades of accumulated experience in test engineering and mass production,

We tailor-make the perfect testing solutions for our clients.

 

Mr. Wayne | Email: wayne@sigurd.com.tw

 

 

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